LM4548 datasheet(12/18 Pages) NSC

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Application Information

AC Link Serial Interface Protocol

AC Link Output Frame: SDATA_OUT (output from

controller, input to LM4548)

The audio output frame (output from AC ’97 Controller) con-

tains control and PCM data targeted for the LM4548 control

registers and stereo DAC. The Tag slot, slot 0, contains 16

bits that tell the AC Link interface circuitry on the LM4548 the

validity of the following data slots.

A new audio output frame is signaled with a low to high tran-

sition of SYNC. SYNC is synchronous to the rising edge of

BIT_CLK. On the next rising edge of BIT_CLK, the AC ’97

Controller drives SDATA_OUT with the first bit of slot 0. The

LM4548 samples SDATA_OUT on the falling edge of BIT-

_CLK. The AC ’97 Controller will continue outputting the

SDATA_OUT stream on each successive rising edge of BIT-

_CLK.

SDATA_OUT Slot 0: Tag Phase

The first bit of slot 0 is designated the

″Valid Frame″ bit. If

this bit is 1, it indicates that the current data frame contains

at least one slot of valid data and the LM4548 will further

sample the next four bits to determine which frames do in

fact have valid data. Valid slots are signified bya1in their re-

spective slot bit position.

Bit

Description

Comment

Valid Frame

1 = This frame has valid

data.

Control

address

1 = Control Address is

valid.

Control

1 = Control Data is valid.

Left Playback

PCM Data

1 = Left PCM Data is

valid.

DS100987-4

FIGURE 3. AC 97 Bidirectional Audio Frame

DS100987-6

FIGURE 4. AC Link Audio Output Frame

DS100987-5

FIGURE 5. Start of Audio Output Frame

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