CS8406-CSZ datasheet(7/39 Pages) CIRRUS

7 / 39 page

DS580F6

CS8406

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)

Notes:

9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is dic-

tated by the timing requirements necessary to access the Channel Status and User Bit buffer memory.

Access to the control register file can be carried out at the full 6 MHz rate.

10. Tsch must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns.

11. Data must be held for sufficient time to bridge the transition time of CCLK.

12. For fsck < 1 MHz.

Parameter

Symbol

Min

Typ

Max

Units

CCLK Clock Frequency

(Note 9)

fsck

6.0

MHz

CS High Time Between Transmissions

tcsh

1.0



CS Falling to CCLK Edge

tcss

CCLK Low Time

tscl

CCLK High Time

(Note 10)

tsch

MAX ((1/256 FS + 8), 66)

CDIN to CCLK Rising Setup Time

tdsu

CCLK Rising to DATA Hold Time

(Note 11)

tdh

CCLK Falling to CDOUT Stable

tpd

Rise Time of CDOUT

tr1

Fall Time of CDOUT

tf1

Rise Time of CCLK and CDIN

(Note 12)

tr2

100

Fall Time of CCLK and CDIN

(Note 12)

tf2

100

t r2

t f2

t dsu

t dh

t sch

t scl

CCLK

CDIN

t css

t pd

CDOUT

tcsh

Figure 3. SPI Mode Timing

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