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SI7050 Datasheet(PDF) 21 Page - Silicon Laboratories |
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SI7050 Datasheet(HTML) 21 Page - Silicon Laboratories |
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21 / 26 page ![]() Si7050/1/3/4/5-A20 Rev. 1.14 21 10. PCB Land Pattern and Solder Mask Design Figure 4. Si705x PCB Land Pattern Table 14. PCB Land Pattern Dimensions Symbol mm C1 2.90 E1.00 P1 1.60 P2 2.50 X1 0.45 Y1 0.85 Notes: General 1. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 7. A 2x1 array of 1.00 mm square openings on 1.30 mm pitch should be used for the center ground pad to achieve a target solder coverage of 50%. Card Assembly 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. |
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