4

PS8382B

03/20/02

Introduction

Because of today’s high-speed design demands, board designers

must have extensive knowledge concerning transmission line

effect, EMI, and crosstalk. They also need to understand board

materials, signal and power stacking, connectors, cables, vias, and

trace dimensions. Pericom Semiconductor Corporation offers an

extensive line of high-speed clock products for desktop, notebook,

set top boxes, information device, servers, and workstations. To

make high-speed chips function properly, a designer needs to rely

on accurate schematics and layout guidelines.

This application note focuses on Pericom’s PI6C2502 Zero- Delay

Clock Buffer, presenting schematics and layout guidelines for the

chip. Also listed are some decoupling guidelines that are important

for this chip’s varied applications.

DecouplingCapacitors

Every printed circuit board needs large bypass capacitors to

balance the inductance of the power-supply wiring. These capaci-

tors have some lead inductance that increase as the frequency goes

higher, which is why it is very important to place the capacitors as

To reduce the series lead inductance effect, avoid the following:

1.Long traces larger than 0.

01 inch between capacitor pad and via

2.Use of capacitors other than surface mount

3.Via holes less than 0.

035-inch diameter

Pericom’sclocksusehigh-precision,integratedanalogPLLthatcan

be effected by the power supply and ground pins. Noise on these

two pins can dramatically increase skew and output jitter.

To minimize these problems, connect a 4.7µF, a 220nF , and a 2.2nF

capacitor to the digital supply pin. Also use one 4.7µF , one 220nF,

and one 2.2nF capacitor on the analog supply pin. Connect the other

side to the analog ground pin.

Place a10µFcapacitorfromthemainpowerislandtothepowerplane

that is supplied to the clock chip.

Use high-quality, low ESR, ceramic surface-mount capacitors.

Stacking

At low speeds, currents follow the least resistance path, but at high

speeds current follows the least inductance path. The lowest

inductance return path lies directly under the signal conductor.

Application Note

Layout and Schematic Guidelines

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PI6C2502

Phase-Locked Loop Clock Driver

This location minimizes the total loops needed between the outgo-

ing and returning paths. That is why it is important to separate the

signal layers by ground planes if possible. Also avoid totally

cutting part of the ground plane to be used for a signal’s path. That

is totally unacceptable, because it will increase crosstalk consider-

ably and does not provide a clean return to those signals. Also use

lower trace impedance because it lowers undershoot and over-

shoot. Always use FR-4 material for board fabrication. Use 4- layer

stack-up arrangement. Make sure you have a signal layer that is

followed by the ground layer, then a power layer, and finally the

second signal layer. Please see Figure 1 below.

Primary Signal

Layer (½ oz. cu.)

Ground Plane

(1 oz. cu.)

5 mils

47 mils

5 mils

PREPREG

CORE

Z = 60 Ohms

Z = 60 Ohms

Total Board Thickness = 62.6

PREPREG

Power Plane

(1 oz. cu.)

Secondary Signal

Layer (½ oz. cu.)

Figure1:Four-LayerBoardStack-up

Figure 2: Clock Trace Spacing Guidelines

Clock routing and spacing

To minimize crosstalk on the clock signals, use a minimum of

0.014-inch spacing between clock traces and others. If you have to

use serpentine to match trace lengths on similar chips, make sure

that you have at least 0.018-inch spacing for serpentines. Please see

Figure 2 below.

0.014"

0.018"

Clock