PCF85 datasheet(12/24 Pages) ICST

12 / 24 page

1997 Feb 13

Philips Semiconductors

Product speciﬁcation

256 to 1024

× 8-bit CMOS EEPROMs with

I2C-bus interface

PCF85xxC-2 family

11 I2C-BUS CHARACTERISTICS

All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and

VIH with an input voltage swing from VSS to VDD; see Fig.10.

Note

1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be

internally provided by a transmitter.

SDA input/output (pin 5)

VIL

LOW level input voltage

−0.8

0.3VDD

VIH

HIGH level input voltage

0.7VDD

+6.5

VOL

LOW level output voltage

IOL = 3 mA; VDD(min)

−

0.4

ILO

output leakage current

VOH =VDD

−

µA

input capacitance

VI =VSS

−

7pF

Data retention time

data retention time

Tamb =55 °C10

−

years

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

fSCL

clock frequency

100

kHz

tBUF

bus free time between a STOP and START

condition

4.7

−µs

tHD;STA

START condition hold time after which ﬁrst clock

pulse is generated

4.0

−µs

tLOW

LOW level clock period

4.7

−µs

tHIGH

HIGH level clock period

4.0

−µs

tSU;STA

set-up time for STARt condition

repeated start

4.7

−µs

tHD;DAT

data hold time

for bus compatible masters

−µs

for bus devices

note 1

−

tSU;DAT

data set-up time

250

−

SDA and SCL rise time

−

µs

SDA and SCL fall time

−

300

tSU;STO

set-up time for STOP condition

4.0

−µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

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