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ICS9DB108 Datasheet(PDF) 2 Page - Integrated Circuit Systems

Part # ICS9DB108
Description  Eight Output Differential Buffer for PCI-Express
PDF  15 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9DB108 Datasheet(HTML) 2 Page - Integrated Circuit Systems

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Integrated
Circuit
Systems, Inc.
ICS9DB108
0723D—01/08/04
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
SRC_DIV#
IN
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
2
VDD
PWR
Power supply, nominal 3.3V
3
GND
PWR
Ground pin.
4
SRC_IN
IN
0.7 V Differential SRC TRUE input
5
SRC_IN#
IN
0.7 V Differential SRC COMPLEMENTARY input
6OE_0
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
7OE_3
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
8
DIF_0
OUT
0.7V differential true clock outputs
9
DIF_0#
OUT
0.7V differential complement clock outputs
10
GND
PWR
Ground pin.
11
VDD
PWR
Power supply, nominal 3.3V
12
DIF_1
OUT
0.7V differential true clock outputs
13
DIF_1#
OUT
0.7V differential complement clock outputs
14
OE_1
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
15
OE_2
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
16
DIF_2
OUT
0.7V differential true clock outputs
17
DIF_2#
OUT
0.7V differential complement clock outputs
18
GND
PWR
Ground pin.
19
VDD
PWR
Power supply, nominal 3.3V
20
DIF_3
OUT
0.7V differential true clock outputs
21
DIF_3#
OUT
0.7V differential complement clock outputs
22
BYPASS#/PLL
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
24
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.



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