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MB91F577CSPMC Datasheet(PDF) 123 Page - Cypress Semiconductor |
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MB91F577CSPMC Datasheet(HTML) 123 Page - Cypress Semiconductor |
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123 / 163 page  Document Number: 002-04725 Rev.*A Page 123 of 163 MB91570 Series Bit setting: SMR: MD2 = 0, SMR: MD1 = 1, SMR: MD0 = 0, SMR: SCINV = 1, SCR: SPI = 0 (TA: Recommended operating conditions, VCC5 = 5.0V±10%, VCCE = 5.0V±10%, VSS = AVSS = 0.0V) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0, SCK1, SCK8, SCK9 – 4tCPP – ns Internal shift clock mode: CL = 50pF (When drive capability is 2mA or more.) CL = 20pF(When drive capability is 1mA) SCK ↑ → SOT delay time tSHOVI SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, SOT8, SOT9 -30 +30 ns Valid SIN → SCK ↓setup time tIVSLI SCK0, SCK1, SCK8, SCK9, SIN0, SIN1, SIN8, SIN9 34 – ns SCK ↓ → Valid SIN hold time tSLIXI 0 – ns Serial clock "H" pulse width tSHSL SCK0, SCK1, SCK8, SCK9 – tCPP+10 – ns External shift clock mode: CL = 50pF (When drive capability is 2mA or more.) CL = 20pF(When drive capability is 1mA) Serial clock "L"pulse width tSLSH 2tCPP-10 – ns SCK ↑ → SOT delay time tSHOVE SCK0, SCK1, SCK8, SCK9, SOT0, SOT1, SOT8, SOT9 – 33 ns Valid SIN → SCK ↓setup time tIVSLE SCK0, SCK1, SCK8, SCK9, SIN0, SIN1, SIN8, SIN9 10 – ns SCK ↓ → Valid SIN hold time tSLIXE 20 – ns SCK fall time tF SCK0, SCK1, SCK8, SCK9 – 5 ns SCK rise time tR SCK0, SCK1, SCK8, SCK9 – 5 ns Notes: • AC characteristic in CLK synchronized mode. • CL is the load capacitance applied to pins during testing. • The maximum baud rate is limited by the internal operation clock used and other parameters. Refer to Hardware Manual for details. |
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