SSD1815 datasheet(7/35 Pages) ETC

7 / 35 page

SOLOMON

SSD1815

REV 1.5

03/2000

This pin is the input of the built-in voltage regulator. When exter-

nal resistor network is selected to generate the LCD driving level,

VL6, two external resistors, R1 and R2, are connected between VDD

and VF, and VF and VL6, respectively (see application circuit).

M/S

This pin is the master/slave mode selection input. When this pin

is pulled high, master mode is selected, which CL, M, MSTAT and

DOF signals will be output for slave devices. When this pin is

pulled low, slave mode is selected, which CL, M, DOF are required

to be input from master device and MSTAT is high impedance.

CLS

This pin is the internal clock enable pin. When this pin is pulled

high, internal clock is enabled. The internal clock will be disabled

when it is pulled low, an external clock source should be input to

CL pin.

C68/80

This pin is microprocessor interface selection input. When the

pin is pulled high, 6800 series interface is selected and when the

pin is pulled low, 8080 series MCU interface is selected.

P/S

This pin is serial/parallel interface selection input. When this pin

is pulled high, parallel mode is selected. When it is pulled low,

serial interface will be selected. Read back operation is only avail-

able in parallel mode.

HPM

This pin is the control input of High Power Current Mode. The

function of this pin is only enabled for High Power model which

required special ordering.

For normal models, High Power Mode is disabled and the LCD

driving characteristics are the same no matter this pin is pulled

High or Low.

Note: This pin must be pulled to either High or Low. Leaving this

pin floating is prohibited.

IRS

This is the input pin to enable the internal resistors network for

the voltage regulator. When this pin is pulled high the internal resis-

tors will be enalbed, and when it is low, the external resistors, R1

and R2, should be connected to VDD and VF, and VF and VL6,

respectively (see application circuits).

ROW0 - ROW63

These pins provide the row driving signal COM0 - COM63 to the

LCD panel. See Table.1 about the COM signal mapping in different

multiplex ratio N.

SEG0 - SEG131

These pins provide the LCD column driving signals. Their output

voltage level is VDD during sleep mode and standby mode.

ICONS

There are two ICONS pins (pin12 and 136) on the chip. Both

pins output exactly the same signal. The reason for duplicating the

pin is to enhance the flexibility of the LCD layout.

These are the No Connection pins. Nothing should be con-

nected to these pins, nor they are connected together. These pins

should be left open individually.

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