UT80C196 datasheet(37/42 Pages) AEROFLEX

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of Timer3 can be found in locations 0Fh (high byte), and 0Eh

(low byte) of HWindow 1.

1.15 Input/Output Pullup/Pulldown Currents

Leakage currents may not meet the industry standard

80C196KD specs due to differently sized weak pullups/

pulldowns, during Quasi-Bidirectional and reset/powerdown

modes. Refer to specs for ILI1 and ILI2.

1.16 Power-down exit

Pin 37 will not be used to exit power-down mode. Since a digital

clock is supplied, no connection between this Vpp pin and the

power-down circuitry exists.

1.17 Test Mode Entry

Test mode entry will be via four pins: WR, RD, ALE andHLDA

instead of PWM0.

1.18 Power-on Reset

The UT80C196KD will not guarantee the 16-state "pulse

stretching" function of a Reset_n pulse applied at power-up. The

user must hold Reset_n low until the power and clocks stabilize

plus 16-state times, or provide a high to low transition after the

power and clocks have stabilized.

1.19 Pullup/Pulldown states

The INST pin will be driven to a weak low during Reset. The

ALE signal will be driven to a weak high during Bus Hold.

1.20 Modifying the INT_PEND registers

Two operand rd-modify-wr instructions should be used to

modify the INT_PEND registers. Three operand rd-modify-wr

instructions may lose an incoming interrupt.

1.21 Serial Port Synchronous Mode

The last clock rising edge to output float time (TXHQZ) is made

consistent with the output data hold (TXHQX) time of 2 TOSC

+/-50nsec. This is longer than the industry standard of 1 TOSC

max.

1.22 Industry Standard Register Indirect with Auto Incre-

ment

The industry standard 80C196KD increments the auto-incre-

mented register after determining the external address instead

of at the end of the instruction completion. The UT80C196KD

performs the auto-increment function at the end of the instruc-

tion processing. Please reference the example below that

shows the processing difference between the UT80C196KD

and the industry standard 80C196KD:

ST R0, [R0]+

assume R0 holds the value 1000h before the instruction is exe-

cuted.

1.23 AC Timing Differences

There are some AC timing differences between the

UT80C196KD and the industry standard 80C196KD. Most

changes resulted in loosened timing specifications. However,

the tRHDZ and tRXDX timing specifications were tightened by

5ns. If you have been designing to the industry standard

80C196KD timing specifications, it is important to recognize

these two shortened timing specifications.

NOTE: Please visit the UTMC website at www.utmc.com to

obtain the latest data sheet updates, application notes, software

examples, advisories and erratas for the UT80C196KD.

1.24 T2UP-DN Input Signal

Port 2.6 has an alternate function of T2UP-DN enabled by

IOC2.1. The industry standard device appears to allow writes

into Port 2.6 to directly affect the pin state when in the T2UP-

DN mode. (This would allow software control of the T2 direc-

tion, but requires ensuring a one (QBD pullup) is written to

Port 2.6 if the pin is driven externally). The UT80C196KD

device is designed to disable the Port 2.6 output when T2UP-

DN is enabled. This protects the P2.6/T2UP-DN pin from con-

tention with an externally driven signal, independent of the

value written into Port 2.

1.25 NEG 8000h Instruction Operation

The UT80CRH196KD and the industry standard 80C196KD

set the N-Flag differently when executing the NEG 8000h

instruction. NEG represents the MCS-96 opcode to negate a

defined operand (8000h). When the UT80CRH196KD exe-

cutes the NEG 8000h instruction, the result becomes 8000h

with both the N-Flag and the V-Flag set. The industry stan-

dard 80C196KD, however, executes the NEG 8000h instruc-

tion with a result of 8000h and only the V-Flag set.

PROCESSING FLOW FOR THE ST R0, [R0]+

INSTRUCTION

UT80C196KD

Industry Standard

80C196KD

Address = [R0]; 1000h

R0 ---> Address

R0 = R0+1; 1001h

R0 ---> Address

* The contents in address

1000h are 1000h

* The contents in address

1000h are 1001h

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