STBCFG01 datasheet(6/37 Pages) STMICROELECTRONICS

6 / 37 page

Pin configuration

STBCFG01

6/37

DocID026474 Rev 3

Pin configuration

Figure 2: Pin connections (top view)

Table 2: Pin description

Symbol

Ball

Pin function

Description

PMID

A1, B1

Power I/O

Reverse blocking MOSFET to high-side connection node

DCIN

A2, A3

Power I/O

Input supply voltage/OTG output

AGND

Analog ground

VCELL-

Analog input

Battery pack negative terminal sense input

CENn

Digital input

Charger enable, active low. Internal 200 kΩ pull-down to

GND

SHDN

Digital input

Shutdown input, active high. Internal 200 kΩ pull-down to

GND

RID

Analog input

Battery identification resistor connection (for battery

detection). An external bias has to be applied

VCELL+

Analog input

Battery pack positive terminal sense input

C1, D1

Power I/O

Switch mode, inductor connection

IRQn

Digital input

Open drain interrupt output, active low

DGND

Digital ground

1V8

Analog out

1.8 V internal regulator bypass pin. Bypass this pin to GND

with a capacitor of 220 nF. Do not connect any load

VREF

Analog out

Reference voltage bypass pin. Do not connect any load

LDO

Analog out

4.85 V LDO output

SDA

Digital I/O

I²C data pin to the baseband, I²C master peripheral

SCL

Digital input

I²C clock pin to the baseband, I²C master peripheral

R_SNS_N

D5, E5

Power I/O

Internal sense resistor, negative terminal

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