Typical Supply Current

vs Supply Voltage

Standby Interrupt

during Power Down

Typical Characteristics

TLF11070 – 4

TLF11070 – 5

FIGURE 2

Symbol

Parameter

Min

Max

Units

Status Register Clock to INTERRUPT OUTPUT

5

m

s

(Pin 13) High (Note 1)

Compare Valid to STANDBY INTERRUPT

5

m

s

(Pin 14) Low (Note 1)

Trailing Edge of Status Register

5

m

s

Read to INTERRUPT OUTPUT Low

Trailing Edge of Write Cycle

5

m

s

INTERRUPT Off (High Impedance State)

Note 1

The status register clocks are the corresponding counter’s rollover to its reset state or the compare becoming valid The compare becomes valid 61 ms

after the 110000 of a second counter is clocked if the real time counter data matches the RAM data

Symbol

Parameter

Min

Max

Units

Address Bus Valid to Read Strobe (Note 3)

100

ns

Chip Select to Read Strobe (Note 2)

0

ns

Read Strobe to Ready Strobe

150

ns

Ready Strobe to Data Valid

800

ns

Address Bus Valid to Data Valid

1050

ns

Data Hold Time from Trailing Edge of Read Strobe

0

ns

Trailing Edge of Read Strobe to TRI-STATE Mode

250

ns

Read Hold Time after Ready Strobe

0

ns

Address Bus Hold Time from Trailing Edge of Read Strobe

50

ns

Rising Edge of Ready to Data Valid

100

ns

Note 2

Note 3

6