NSC800V datasheet(53/76 Pages) NSC

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1212 InputOutput (Continued)

OUT

(n) A

Output the Accumulator to the IO device at address n

(n)

w A

No flags affected

76543210

11010011

Timing

M cycles

T states

11 (4 3 4)

Addressing Mode

Source

Destination

Direct

OUTD

Data is output from memory location (HL) to the IO device

at port address (C) and the HL memory pointer and byte

counter B are decremented

(C)

w (HL)

S Undefined

w B b 1

Z Set if Bb1e0 otherwise reset

w HL b 1

H Undefined

PV Undefined

N Set

C NA

76543210

11101101

10101011

Timing

M cycles

T states

16 (4 5 3 4)

Addressing Mode

ImpliedSource

direct

Destination

INIR

Data is input from the IO device at port address (C) to

memory location (HL) the HL memory pointer is increment-

ed and the byte counter B is decremented The cycle is

repeated until B e 0

(Note that B is tested for zero after it is decremented By

loading B initially with zero 256 data transfers will take

place)

(HL)

w (C)

S Undefined

w HL a 1

Z Set

w B b 1

H Undefined

Repeat until B e 0

PV Undefined

N Set

C NA

76543210

11101101

10110010

Timing

For B i 0

M cycles

T states

21 (4 5 3 4 5)

For B e 0

M cycles

T states

16 (4 5 3 4)

Addressing Mode

ImpliedSource

direct

Destination

(Note that at the end of each data transfer cycle interrupts

may be recognized and two refresh cycles will be per-

formed)

OTIR

Data is output to the IO device at port address (C) from

memory location (HL) the HL memory pointer is increment-

ed and the byte counter B is decremented The cycles are

repeated until B e 0

(Note that B is tested for zero after it is decremented By

loading B initially with zero 256 data transfers will take

place)

(C)

w (HL)

S Undefined

w HL a 1

H Undefined

w B b 1

Z Set

Repeat until B e 0

PV Undefined

N Set

C NA

76543210

11101101

10110011

Timing

For B i 0

M cycles

T states

21 (4 5 3 4 5)

For B e 0

M cycles

T states

16 (4 5 3 4)

Addressing Mode

ImpliedSource

direct

Destination

(Note that at the end of each data transfer cycle interrupts

may be recognized and two refresh cycles will be per-

formed)

NSC800V Datasheet(PDF) 53 Page - National Semiconductor (TI)

NSC800V Datasheet(HTML) 53 Page - National Semiconductor (TI)

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