CDCE937_17 datasheet(5/39 Pages) TI1

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CDCE937, CDCEL937

www.ti.com

SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016

Product Folder Links: CDCE937 CDCEL937

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(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3)

SDA and SCL can go up to 3.6 V as stated in Recommended Operating Conditions.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Supply voltage, VDD

–0.5

2.5

Input voltage, VI

(2) (3)

–0.5

VDD + 0.5

Output voltage, VO

(2)

–0.5

Vddout + 0.5

Input current, II (VI < 0, VI > VDD)

Continuous output current, IO

Junction temperature, TJ

125

°C

Storage temperature, Tstg

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±1500

(1)

For more information about VCXO configuration, and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family

(SCAA085).

(2)

Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm

applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).

6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

VDD

Device supply voltage

1.7

1.8

1.9

Output Yx supply voltage, Vddout

CDCE937

2.3

3.6

CDCEL937

1.7

1.9

VIL

Low-level input voltage LVCMOS

0.3 × VDD

VIH

High-level input voltage LVCMOS

0.7 × VDD

VI(thresh)

Input voltage threshold LVCMOS

0.5 × VDD

VIS

Input voltage

1.9

S1, S2, SDA, SCL,

VI(thresh) = 0.5 VDD

3.6

VI(CLK)

Input voltage, CLK

1.9

IOH /IOL

Output current

Vddout = 3.3 V

±12

Vddout = 2.5 V

±10

Vddout = 1.8 V

±8

Output load LVCMOS

Operating free-air temperature

–40

°C

CRYSTAL AND VCXO(1)

fXtal

Crystal input frequency (fundamental mode)

MHz

ESR

Effective series resistance

100

fPR

Pulling (0 V

≤ Vctrl ≤ 1.8 V)(2)

±120

±150

ppm

Frequency control voltage, Vctrl

VDD

C0/C1

Pullability ratio

220

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