EM357-RTR datasheet(136/241 Pages) SILABS

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Rev 1.3

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9.3.12. Timer Input XOR Function

The TIM_TI1S bit in the TIM1_CR2 register allows the input filter of channel 1 to be connected to the output of a

XOR gate that combines the three input pins TIMxC2 to TIMxC4.

The XOR output can be used with all the timer input functions such as trigger or input capture. It is especially useful

to interface to Hall effect sensors.

9.3.13. Timers and External Trigger Synchronization

The timers can be synchronized with an external trigger in several modes: reset mode, gated mode, and trigger

mode.

9.3.13.1. Slave Mode: Reset Mode

Reset mode reinitializes the counter and its prescaler in response to an event on a trigger input. Moreover, if the

TIM_URS bit in the TIMx_CR1 register is low, a UEV is generated. Then all the buffered registers (TIMx_ARR,

TIMx_CCRy) are updated.

In the following example, the up-counter is cleared in response to a rising edge on the TI1 input:



Configure the channel 1 to detect rising edges on TI1:



Configure the input filter duration. In this example, no filter is required so TIM_IC1F = 0000.



The capture prescaler is not used for triggering, so it is not configured.



The TIM_CC1S bits select the input capture source only, TIM_CC1S = 01 in the TIMx_CCMR1 register.



Write TIM_CC1P = 0 in the TIMx_CCER register to validate the polarity, and detect rising edges only.



Configure the timer in reset mode: Write TIM_SMS = 100 in the TIMx_SMCR register.



Select TI1 as the input source by writing TIM_TS = 101 in the TIMx_SMCR register.



Start the counter: Write TIM_CEN = 1 in the TIMx_CR1 register.

The counter starts counting on the internal clock, then behaves normally until the TI1 rising edge. When TI1 rises,

the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (the INT_TIMTIF bit in the

INT_TIMxFLAG register) and an interrupt request can be sent if enabled (depending on the INT_TIMTIF bit in the

INT_TIMxCFG register).

Figure 9.27 shows this behavior when the auto-reload register TIMx_ARR = 0x36. The delay between the rising

edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on the TI1 input.

Figure 9.27. Control Circuit in Reset Mode

EM357-RTR Datasheet(PDF) 136 Page - Silicon Laboratories