L99MD01 datasheet(24/54 Pages) STMICROELECTRONICS

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Functional description of the SPI

L99MD01

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Doc ID 17242 Rev 6

5.2

SPI communication flow

5.2.1

General description

The proposed SPI communication is based on a standard SPI interface structure using CSN

(Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock)

signal lines. Maximum SPI frequency is 1 MHz.

At the beginning of each communication the master reads the <SPI-frame-ID> register

(ROM address 3EH) of the slave device. This 8-bit register indicates the SPI frame length

(24-bit for the L99MD01) and the availability of additional features.

Each communication frame consists of an instruction byte which is followed by 2 data bytes

(see

Figure 8).

The data returned on SDO within the same frame always starts with the <Global Status>

‘In-frame-response’, Figure 8).

For write cycles the <Global Status> register is followed by the previous content of the

addressed register.

For read cycles the <Global Status> register is followed by the content of the addressed

5.2.2

Command byte

Each communication frame starts with a command byte. It consists of an operating code

which specifies the type of operation (<Read>, <Write>, <Read and Clear Status>, <Read

Device Information>) and a 6 bit address.

Table 18.

Command byte (8 bit)

Operating code

Address

Bit

23222120

1918

Name

OC1

OC0

Table 19.

Data byte

Data byte 1

Data byte 0

Bit

9876

543

210

Name D15 D14 D13 D12 D11 D10

Table 20.

Operating code definition

OC1

OC0

Meaning

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