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TNETV6446AINZWT Datasheet(PDF) 148 Page - Texas Instruments |
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TNETV6446AINZWT Datasheet(HTML) 148 Page - Texas Instruments |
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148 / 227 page  DMARQ HSTROBE (DIOR) (A) STOP (DIOW) (A) DDMARDY (IORDY) (A) DD[15:0] DMACK DA[2:0], ATA_CS0, ATA_CS1 tUI tZIORDY tENV tACK tACK tACK tDZFS tLI tUI tDVS tDVH HSTROBE (DIOR) DD[15:0] (OUT) t2CYC tCYC(A) tCYC(A) t2CYC tDVH tDVS tDVH tDVS tDVH TMS320DM6446 SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com A. The definitions for the DIOW:STOP, IORDY:DDMARDY, and DIOR:HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 6-33. ATA/CF Initiating an Ultra DMA Data-Out Burst Timing A. While HSTROBE (DIOR) timing is tCYC at the host, it may be different at the device due to propagation delay differences on the cable. Figure 6-34. ATA/CF Sustained Ultra DMA Data-Out Transfer Timing 148 Peripheral and Electrical Specifications Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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