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TNETV6446AINZWT Datasheet(PDF) 74 Page - Texas Instruments |
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TNETV6446AINZWT Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 227 page  TMS320DM6446 SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com Table 3-14. PINMUX0 Register Description (continued) Name Description AECS4 Enable EMIFA EM_CS4 function on GPIO[9] AEAW EMIFA address width selection. Default value is latched at reset from AEAW[4:0] configuration input pins. This enables EMIF address function on default GPIO[10:28] pins. 3.5.5 PINMUX1 Register Description The PINMUX1 pin multiplexing register controls which peripheral is given ownership over shared pins among Timer, PLL, ASP, SPI, I2C, PWM, and UART peripherals. The register format is shown in Figure 3-8 and bit field descriptions are given in Table 3-15. More details on the PINMUX1 pin muxing fields are given in Section 3.5.6, Pin Multiplexing Register Field Details. A value of "1" enables the secondary or tertiary pin function. Figure 3-8. PINMUX1 Register(1) 31 19 18 17 16 Reserved TIMIN CLK1 CLK0 R-0000 0000 0000 0 R/W-0 R/W-0 R/W-0 15 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ASP Rsvd SPI I2C PWM2 PWM1 PWM0 U2FLO UART2 UART1 UART0 R-0000 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset (1) For proper DM6446 device operation, always write a value of '0' to RSV bit 9. Table 3-15. PINMUX1 Register Description Name Description TIMIN Enable TIM_IN function on default GPIO[49] pin CLK1 Enable CLK_OUT1 function on default GPIO[49] pin CLK0 Enable CLK_OUT0 function on default GPIO[48] pin ASP Enable ASP function on default GPIO[29:34] pins SPI Enable SPI function on default GPIO[37,39:42] pins I2C Enable I2C function on default GPIO[43:44] pins PWM2 Enable PWM2 function on default GPIO[47] pin PWM1 Enable PWM1 function on default GPIO[46] pin PWM0 Enable PWM0 function on default GPIO[45] pin U2FLO Enable UART2 flow control function on default VPFE CI[5:4]/CCD_DATA[13:12] pins UART2 Enable UART2 function on default VPFE CI[7:6]/CCD_DATA[15:14] pins UART1 Enable UART1 function on shared ATA (CF) DMACK, DMARQ pins UART0 Enable UART0 function on default GPIO[35:36] pins 74 Device Configurations Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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