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TNETV6446AINZWT Datasheet(PDF) 159 Page - Texas Instruments

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Part # TNETV6446AINZWT
Description  Digital Media System-on-Chip
PDF  227 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TNETV6446AINZWT Datasheet(HTML) 159 Page - Texas Instruments

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TMS320DM6446
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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
6.13.1.2 Preview Engine
The preview engine transforms raw unprocessed image/video data from a sensor (CMOS or CCD) into
YCbCr 4:2:2 data. The output of the preview engine is used for both video compression and external
display devices such as a NTSC/PAL analog encoder or a digital LCD. The following features are
supported by the preview engine.
•
Accepts conventional Bayer pattern formats.
•
Input image/video data from either the CCD/CMOS controller or the DDR2 memory.
•
Output width up to 1280 pixels wide.
•
Automatic/mandatory cropping of pixels/lines when edge processing is performed. If all the
corresponding modules are enabled, a total of 14 pixels per line (7 left most and 7 right most) and 8
lines (4 top most and 4 bottom most) will not be output.
•
Simple horizontal averaging (by factors of 2, 4, or 8) to handle input widths that are greater than 1280
(plus the cropped number) pixels wide.
•
Dark frame capture to DDR2.
•
Dark frame subtraction for every input raw data frame, fetched from DDR2, pixel-by-pixel to improve
video quality.
•
Lens shading compensation. Each input pixel is multiplied with a corresponding 8-bit gain value and
the result is right shifted by a programmable parameter (0-7 bits).
•
A-law decompression to transform non-linear 8-bit data to 10-bit linear data. This feature allows data in
DDR2 to be 8-bits, which saves 50% of the area if the input to the preview engine is from the DDR2.
•
Horizontal median filter for reducing temperature induced noise in pixels.
•
Programmable noise filter that operates on a 3x3 grid of the same color (effectively, this is a five line
storage requirement).
•
Digital gain and white balance (color separate gain for white balance).
•
Programmable CFA interpolation that operates on a 5x5 grid.
•
Conventional Bayer pattern RGB and complementary color sensors.
•
Support for an image that is downsampled by 2x in the horizontal direction (with and without phase
correction). In this case, the image is 2/3 populated instead of the conventional 1/3 colors.
•
Support for an image that is downsampled by 2x in both the horizontal and vertical direction. In this
case, the image is fully populated instead of the conventional 1/3 colors.
•
Programmable RGB-to-RGB blending matrix (9 coefficients for the 3x3 matrix).
•
Fully programmable gamma correction (1024 entries for each color held in an on-chip RAM).
•
Programmable color conversion (RGB to YUV) coefficients (9 coefficients for the 3x3 matrix).
•
Luminance enhancement (non-linear) and chrominance suppression & offset.
The Preview Engine register memory mapping is shown in Table 6-49.
Copyright © 2005–2010, Texas Instruments Incorporated
Peripheral and Electrical Specifications
159
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Product Folder Link(s): TMS320DM6446



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