LNBH24L

I²C bus interface

Doc ID 16857 Rev 2

13/25

6

I²C bus interface

Data transmission from main microprocessor to the LNBH24L and vice versa takes place

through the 2 wires I²C bus interface, consisting of the 2 lines SDA and SCL (pull-up

resistors to positive supply voltage must be externally connected).

6.1

Data validity

As shown in Figure 6, the data on the SDA line must be stable during the high semi-period

of the clock. The HIGH and LOW state of the data line can only change when the clock

signal on the SCL line is LOW.

6.2

Start and stop condition

As shown in Figure 7 a start condition is a HIGH to LOW transition of the SDA line while

SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is

HIGH. A STOP condition must be sent before each START condition.

6.3

Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an

acknowledge bit. The MSB is transferred first.

6.4

Acknowledge

The master (microprocessor) puts a resistive HIGH level on the SDA line during the

acknowledge clock pulse (see Figure 8). The peripheral (LNBH24L) that acknowledges has

to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is

stable LOW during this clock pulse. The peripheral which has been addressed has to

generate acknowledge after the reception of each byte, otherwise the SDA line remain at the

HIGH level during the ninth clock pulse time. In this case the master transmitter can

generate the STOP information in order to abort the transfer. The LNBH24L won't generate

6.5

Transmission without acknowledge

Avoiding to detect the acknowledges of the LNBH24L, the microprocessor can use a simpler

transmission: simply it waits one clock without checking the slave acknowledging, and sends

the new data. This approach of course is less protected from misworking and decreases the

noise immunity.