ST7FOXU0 datasheet(108/123 Pages) STMICROELECTRONICS

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Electrical characteristics

ST7FOXU0

108/123

12.10

10-bit ADC characteristics

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

Figure 41.

Typical application with ADC

Table 58.

ADC characteristics

Symbol

Parameter

Conditions

Min

Typ(1)

Max

Unit

fADC

ADC clock frequency

MHz

VAIN

Conversion voltage range

VSS

VDD

RAIN

External input resistor

VDD = 5 V, fADC = 4 MHz

8k(2)

Ω

4.5 V

≤ V

DD ≤ 5.5 V, fADC = 2 MHz

10k(2)

CADC

Internal sample and hold

capacitor

3pF

tSTAB

Stabilization time after ADC

enable

CPU = 8 MHz, fADC = 4 MHz

0(3)

µs

tADC

Conversion time (Sample+Hold)

3.5

- Sample capacitor loading time

- Hold conversion time

1/fADC

Unless otherwise specified, typical data are based on TA = 25 °C and VDD-VSS = 5 V. They are given only as design

guidelines and are not tested.

Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maximum

value). Data guaranteed by Design, not tested in production.

The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then always

valid.

AINx

ST7xxx

VDD

±1

µA

0.6 V

CADC

VAIN

RAIN

10-Bit A/D

Conversion

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