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STM8TL52X4 Datasheet(PDF) 32 Page - STMicroelectronics |
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STM8TL52X4 Datasheet(HTML) 32 Page - STMicroelectronics |
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32 / 84 page  Memory and register map STM8TL52x4 STM8TL53x4 32/84 DocID022344 Rev 7 0x00 5280 TIM3 TIM3_CR1 TIM3 control register 1 0x00 0x00 5281 TIM3_CR2 TIM3 control register 2 0x00 0x00 5282 TIM3_SMCR TIM3 slave mode control register 0x00 0x00 5283 TIM3_ETR TIM3 external trigger register 0x00 0x00 5284 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5285 TIM3_SR1 TIM3 status register 1 0x00 0x00 5286 TIM3_SR2 TIM3 status register 2 0x00 0x00 5287 TIM3_EGR TIM3 event generation register 0x00 0x00 5288 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00 0x00 5289 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00 0x00 528A TIM3_CCER1 TIM3 capture/compare enable register 1 0x00 0x00 528B TIM3_CNTRH TIM3 counter register high 0x00 0x00 528C TIM3_CNTRL TIM3 counter register low 0x00 0x00 528D TIM3_PSCR TIM3 prescaler register 0x00 0x00 528E TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 528F TIM3_ARRL TIM3 auto-reload register low 0xFF 0x00 5290 TIM3_CCR1H TIM3 capture/compare register 1 high 0x00 0x00 5291 TIM3_CCR1L TIM3 capture/compare register 1 low 0x00 0x00 5292 TIM3_CCR2H TIM3 capture/compare register 2 high 0x00 0x00 5293 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00 0x00 5294 TIM3_BKR TIM3 break register 0x00 0x00 5295 TIM3_OISR TIM3 output idle state register 0x00 0x00 5296 to 0x00 52DF Reserved area (74 byte) 0x00 52E0 TIM4 TIM4_CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00 0x00 52E3 TIM4_IER TIM4 interrupt enable register 0x00 0x00 52E4 TIM4_SR1 TIM4 Status register 1 0x00 0x00 52E5 TIM4_EGR TIM4 event generation register 0x00 0x00 52E6 TIM4_CNTR TIM4 counter register 0x00 0x00 52E7 TIM4_PSCR TIM4 prescaler register 0x00 0x00 52E8 TIM4_ARR TIM4 auto-reload register low 0xFF Table 7. General hardware register map (continued) Address Block Register label Register name Reset status |
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