50 Configuration Registers

Reg

RW

Description

(HEX)

00 – 01

RW

VENDOR ID

100Bh

02 – 03

RW

DEVICE ID

0002h

04 – 05

RW

COMMAND REGISTER (CMD)

The command register provides coarse control over the device’s ability to

generate and respond to PCI cycles

Bit 0 IO Space This bit is used to enable the device to respond to PCI IO cycles The default value is the

sampled value of the ENABLE pin (sampled on the rising edge of RST )

0 Device is disabled

1 Device is enabled

Bit 1 Not used 0 during reads

Bit 2 Bus Master Controls the device’s ability to act as a master on the PCI bus

0 Device cannot be bus master This will disable all DMA operations even if internal DMA is enabled

(default value)

1 Device can become a bus master If this bit is set and internal DMA is enabled then the device can

become a bus master

Bit 3 – 5 Not used 000 during reads

Bit 6 Parity Error (PERR ) response

0 Ignore parity error (default)

1 Respond to parity error

Bit 7 Not used 0 during reads

Bit 8 System Error (SERR ) response

0 Disable system error checking (default)

1 Enable system error checking

Bit 9 Not used 0 during reads Fast back-to-back transactions to same agent

Bit 10 – 15 Not used 000000 during reads

06 – 07

RW

STATUS REGISTER (SR)

The status register is used to record status information for PCI bus related events

Reads to this register behave normally Writes to this register cause bit(s) to be reset A bit is reset whenever the

register is written with a ‘‘1’’ in the corresponding bit location

Bit 0 – 6 Reserved

Bit 7 Always 0

Bit 8 Data Parity Detected

0 No parity detected

1 Parity detected

Bit 9 – 10 DEVSEL

timing

00 Reserved

01 Medium decode (default)

Bit 11 Signaled Target Abort

0 The device did not terminate a transaction with target abort

1 The device has terminated a transaction with target abort

Bit 12 Receive Target Abort

0 The device has not received a target abort

1 The device has received a target abort when it was a master

Bit 13 Received Master Abort

0 Transaction was not terminated with a master abort

1 Transaction has been terminated with a master abort

Bit 14 Signaled System Error (SERR )

0 System error was not signaled

1 System error was signaled

Bit 15 Detected Parity Error (PERR )

0 No parity error detected

1 Parity error detected

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