CS5521 datasheet(47/56 Pages) CIRRUS

47 / 56 page

CS5521/22/23/24/28

DS317F2

configuration register. Note that while the RS

bit is set to ‘1’ all other register bits in the ADC

will be reset to their default state, and the RS bit

must be set to ‘0’ for normal operation of the

converters.

Once the RS bit has been set to ‘0’, the ADC is

placed in the command state were it waits for a val-

id command to execute. The next step is to load the

configuration register and then the channel setup

registers with conditions that you have decided. If

you need to do a factory calibration, perform offset

and gain calibrations for each channel that is to be

used. Then off-load the offset and gain register

contents into EEPROM. These registers can then

be initialized to these conditions when the instru-

ment is used in normal operation. Once calibration

is ready, input the command to start conversions in

the mode you have selected via the configuration

data is ready and read conversion data.

2.11 PCB Layout

The CS5521/22/23/24/28 should be placed entirely

over an analog ground plane with both the AGND

and DGND pins of the device connected to the an-

alog plane. Place the analog-digital plane split im-

mediately adjacent to the digital portion of the chip.

If separate digital (VD+) and analog (VA+) sup-

plies are used, it is recommended that a diode be

placed between them (the cathode of the diode

should point to VA+). If the digital supply comes

up before the analog supply, the ADC may not start

up properly.

Note: See the CDB5521/22/23/24/28 data sheet for suggest-

ed layout details and Applications Note 18 for more

detailed layout guidelines. Before layout, please call

for our Free Schematic Review Service.

CS5521 Datasheet(PDF) 47 Page - Cirrus Logic