WM9710

Production Data

w

PD Rev 4.0 December 2003

25

SPSA0, SPSA1

SPDIF SLOT MAPPING

00

Slots 3 & 4

01

Slots 7 & 8

10

Slots 6 & 9

11

Slots 10 & 11

Table 16 SPDIF Slot Mapping

REGISTER 2Ch AND 32h – AUDIO SAMPLE RATE CONTROL REGISTERS

These registers are read/write registers that are written to, to select alternative sample rates for

the audio PCM converters. Default is the 48kHz rate. Note that only Revision 2.2 recommended

rates are supported by the WM9710, selection of any other unsupported rates will cause the rate

to default to the nearest supported rate, and the supported rate value to be latched and so read

back. Sample rate is entered in binary form to the appropriate register.

REGISTERS 3AH – SPDIF CONTROL REGISTER

Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields

propagated as channel status (or sub-frame in the V case). With the exception of V, this register

should only be written to when the SPDIF transmitter is disabled (SPDIF bit in register 2Ah is ‘0’).

Once the desired values have been written to this register, the contents should be read back to

ensure that the sample rate in particular is supported, then SPDIF validity bit SPCV in register

2Ah should be read to ensure the desired configuration is valid. Only then should the SPDIF

enable bit in register 2Ah be set. This ensures that control and status information start up

correctly at the beginning of SPDIF transmission. WM9710 only supports an SPDIF sample rate

of 48kHz.

CONTROL

BIT

FUNCTION

PRO

Professional; ‘0’ indicates consumer, ‘1’ indicates professional

AUDIB

Non-audio; ‘0’ indicates data is PCM, ‘1’ indicates non-PCM format (eg DD or DTS)

COPY

Copyright; ‘0’ indicates copyright is not asserted, ‘1’ indicates copyright

PRE

Pre-emphasis; ‘0’ indicates not pre-emphasis, ‘1’ indicates 50/15us pre-emphasis

CC[6-0]

Category code; programmed as required by user

L

Generation level; programmed as required by user

V

Validity bit; ‘0’ indicates frame valid, ‘1’ indicates frame not valid

Table 17 SPDIF Control Register

VENDOR SPECIFIC REGISTERS (INDEX 5Ah - 7Ah)

These registers are vendor specific. Do not write to these registers unless the Vendor ID register

has been checked first to ensure that the controller knows the source of the AC ‘97 component.

MIXER MUTE PATH (INDEX 5AH)

Bit 4 (MPM) is used to disable the path between the main input mixer and the lineout mixer.

Setting this bit to 1, breaks the connection and allows the following combinations:

DAC + PHONE + PCBEEP to line out / headphone out

When writing to this register all bits (except MPM) must be written as a 0 or device function can

not be guaranteed.

VENDOR SPECIFIC MODE CONTROL (INDEX 5CH)

Register 5Ch is a vendor specific control register used to control the function of non-AC’97

specified functions. This register defaults to all special features ‘disabled’ i.e. All zeros.