XR-T56L22

3

Rev. 1.02

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

ALBO FIL

LC BIAS

LC I/P

PHASE CONT.

REG CONT.

CLOCK O/P

ANA GND

ALBO1

ALBO2

AMP-I/P

AMP +I/P

AMP -O/P

AMP +O/P

DIG GND

DATA-

DATA+

18 Lead PDIP, CDIP (0.300”)

18

1

10

9

2

3

4

5

6

7

15

14

13

12

11

17

16

8

ALBO FIL

LC BIAS

LC I/P

PHASE CONT.

ANA GND

ALBO1

ALBO2

AMP-I/P

REG CONT.

VREF

CLOCK O/P

AMP +I/P

AMP -O/P

AMP +O/P

DIG GND

DATA-

DATA+

18 Lead SOIC (Jedec, 0.300”)

PIN DESCRIPTION

Pin #

Symbol

Description

1

ANA GND

Ground for Analog Sections of IC and Substrate.

2

ALBO 1

ALBO PORT 1 Output. Port impedance varies between 25W and 20kW proportional to input signal

level.

3

ALBO 2

ALBO PORT 2 Output. Similar to pin 2.

4

AMP - I/P

Inverting Input of Signal Preamp RIN > 20kW.

5

AMP + I/P

Non-Inverting Input of Signal Preamp. RIN > 20kW.

6

AMP - O/P

Inverting Output of Signal Pre-amp. Rout < 200W. DC level typically 3.2V.

7

AMP + O/P

Non-inverting Output of Signal Pre-amp. Similar to pin 6.

8

DIG GND

Ground for Digital Portion of IC.

9

DATA+

10

DATA-

11

CLOCK O/P

Phase Shifted Clock Output (Open Collector). Decouple to GND with 0.1mF if not required. With

12

Input Pin of Shunt Regulator and Supply Pin for IC. For voltage feed applications the regulator

must be disabled and a 5V + 5% supply connected. For line feed a current of 48-120mA is required.

ICC < 8.75mA @ RON, ALBO = 25W typical.

13

VREF

Output Voltage of Internal Reference of Shunt Regulator. For parallel operation of regulators

0.1mF.

14

REG CONT

Input Voltage of Shunt Regulator Amp. To inhibit regulator, pin should be tied to ground. For line

feed operation decouple to GND with 0.1mF. For parallel operation of regulators tie pin 14 of 2nd

15

PHASE

CONT

Phase Shift Adjust Input. A resistor to GND from the pin allows adjustment of phase shift from 905

to approximately 05. RP typical 1.8K to 1K. Vphase typical 340mV.

16

LC I/P

Clock Amplifier Input. Pulsed with current from clock comparator. Connect LC tank between 16, 17

for clock recovery. Ickon = —110mA typical.

17

LC BIAS

Clock Amplifier Reference Voltage. VLC = 3.6V typical.

18

ALBO FIL

Control Pin for ALBO Ports. Voltage developed across a capacitor on this pin defines ALBO on

impedance VALBO = 1.5V typical.