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USB97CFDC Datasheet(PDF) 13 Page - SMSC Corporation |
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USB97CFDC Datasheet(HTML) 13 Page - SMSC Corporation |
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13 / 20 page  SMSC DS – USB97CFDC Page 13 Rev. 12/15/2000 FA[0:19 ] FD [7:0 nFR D nFW R t1 t5 t3 t4 t2 FIGURE 2 – FLASH READ TIMING Table 3 – Flash Read Timing NAME PARAMETER MIN TYP MAX UNITS t1 FA[14:0] Address setup time to nFRD asserted 40 ns t2 nFRD pulse width 110 ns t3 FD[7:0] Data setup time to nFRD de-asserted 30 ns t4 FD[7:0] Data hold time from nFRD de-asserted 0 ns t5 FA[14:0] Address hold time from nFRD de-asserted 35 ns FIGURE 3 – SRAM MEMORY WRITE TIMING Table 4 – SRAM Memory Write Timing NAME PARAMETER MIN TYP MAX UNITS t1 SA[19:0] valid before nMEMWR asserted 10 ns t2 nMEMWR pulse width 100 ns t3 SD[7:0] Data setup time to nMEMWR de-asserted 50 ns t4 SD[7:0] Data hold time from nMEMWR de-asserted 10 ns t5 nMEMWR de-asserted to SA[13:0] invalid 10 ns SA [1 3 :0 S D [7 :0 nM E M W t1 t5 t3 t4 t2 |
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