ICS93722 datasheet(4/6 Pages) ICST

4 / 6 page

ICS9372 2

0539E—07/18/03

Recommended Operating Conditions

TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Analog / Core Supply Voltage

VDD, AVDD

2.3

2.5

2.7

VIL

VDD/2 - 0.5V

VIH

VDD/2 + 0.5V

Inpu Duty Cycle

IDC

Input max jitter

ITCYC

500

Input Voltage Level

Timing Requirements

TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Clock Frequency

freqop

200

MHz

Input Clock Duty Cycle

dtin

Clock Stabilization

tSTAB

from VDD = 2.5V to 1% target

frequency

100

µs

1. Guaranteed by design, not 100% tested in production.

Switching Characteristics

TA = 0 - 70°C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

66 MHz

120

100 - 200 MHz

66 MHz

110

100 - 200 MHz

Phase Error

t(phase error)

CLK_INT to FB_INT

-150

150

Output to output Skew

Tskew

VT = 50%

100

Pulse Skew

Tskewp

100

VT = 50%, 66 MHz to 100 MHz

49.5

50.5

VT = 50%, 101 MHz to 167 MHz

Single-ended 20 - 80 %

Load = 120

Ω / 12 pF

1. Guaranteed by design, not 100% tested in production.

2. Refers to transistion on non-inverting output.

3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.

This is due to the formula: duty cycle = twH / tC, where the cycle time (tC) decreases as the frequency increases.

Duty Cycle (differential)

1,3

950

Rise Time, Fall Time

tR, tF

450

550

Absolute Jitter

Tjabs

Cycle to cycle Jitter

1,2

Tcyc-cyc

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