DLP2000 datasheet(3/40 Pages) TI1

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DLP2000

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DLPS078 – JULY 2017

Product Folder Links: DLP2000

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5 Pin Configuration and Functions

FQC Package

42-Pin LGA

Bottom View

Pin Functions

TYPE

SIGNAL

DATA

RATE

DESCRIPTION

PACKAGE NET

LENGTH (mm)

NAME

NO.

DATA INPUTS

DATA(0)

J13

Input

LVCMOS

DDR

Input Data Bus.

8.83

DATA(1)

Input

LVCMOS

DDR

Input Data Bus.

7.53

DATA(2)

Input

LVCMOS

DDR

Input Data Bus.

6.96

DATA(3)

Input

LVCMOS

DDR

Input Data Bus.

7.05

DATA(4)

Input

LVCMOS

DDR

Input Data Bus.

7.56

DATA(5)

Input

LVCMOS

DDR

Input Data Bus.

7.07

DATA(6)

J12

Input

LVCMOS

DDR

Input Data Bus.

7.61

DATA(7)

J10

Input

LVCMOS

DDR

Input Data Bus.

7.68

DATA(8)

Input

LVCMOS

DDR

Input Data Bus.

7.31

DATA(9)

Input

LVCMOS

DDR

Input Data Bus.

6.76

DATA(10)

Input

LVCMOS

DDR

Input Data Bus.

8.18

DATA(11)

Input

LVCMOS

DDR

Input Data Bus.

7.81

DCLK

Input

LVCMOS

Input Data Clock.

7.78

CONTROL INPUTS

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