Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Read Truth Table

A

R

Output Next State

Q

Q

K



K



K



K



K



X

1

Deselect

Hi-Z

Hi-Z

V

0

Read

Q0

Q1

Notes:

1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.

2. R is evaluated on the rising edge of K.

3. Q0 and Q1 are the first and second data output transfers in a read.

Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth Table

A

W

BWn

BWn

Input Next State

D

D

K



K



K



K



K

K 

K



K



V

0

0

0

Write Byte Dx0, Write Byte Dx1

D0

D1

V

0

0

1

Write Byte Dx0, Write Abort Byte Dx1

D0

X

V

0

1

0

Write Abort Byte Dx0, Write Byte Dx1

X

D1

X

0

1

1

Write Abort Byte Dx0, Write Abort Byte Dx1

X

X

X

1

X

X

Deselect

X

X

Notes:

1. X = Don’t Care, H = High, L = Low, V = Valid.

2. W is evaluated on the rising edge of K.

3. D0 and D1 are the first and second data input transfers in a write.

4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).

GS81302QT07/10/19/37E-318/300/250/200

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.00e 8/2017

9/28

© 2011, GSI Technology