M830 datasheet(3/6 Pages) ICST

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Micro Networks

324 Clark Street

Worcester, MA 01606

tel: 508-852-5400

fax: 508-852-8456

www.micronetworks.com

M830 Series

Preliminary Specifications

Micro Networks

An Integrated Circuit Systems Company

BLOCK DIAGRAM

The M830 clock and data recovery module has a SAW

VCO based phase-locked loop architecture. The

1.225GHz fundamental VCO is implemented as a

transmission oscillator. The oscillator loop includes

the SAW resonator that has a linear phase with

frequency characteristic, a linear voltage controlled

phase shifter, loop amplifier, and power divider to

couple signal from the loop. The oscillator is

frequency doubled to 2.450GHz and band pass

filtered. The 2.450GHz is then multiplied by five to the

final frequency of 12.25GHz. The output of the VCO is

power divided to provide an input to the phase

detector and a clock signal.

The input data is power divided to provide inputs to

the decision circuit and the clock recovery circuitry.

The input to the clock recovery circuit is amplified and

applied to an analog frequency doubler to extract a

clock spectral component from the NRZ data input

stream. The 12.25GHz doubler output is band pass

filtered and amplified.

One VCO output and the clock extracted from the

input data serve as inputs to a microwave phase

detector. The phase detector output is applied to an

integrator circuit. The integrator output controls the

phase shifter in the SAW VCO, completing the phase-

lock loop. The phase-locked loop causes the low

noise VCO output to be phase-locked to the clock

signal extracted from the NRZ input data, providing a

low jitter clock signal.

The clock signal is applied to a phase shifter that

allows the timing between the input data and clock to

be adjusted for optimum performance. The phase

shifter output is amplified and band pass filtered to

provide a low jitter and low spurious clock. The clock

is power divided to provide the clock output of the

module and the clock input to the decision circuit.

The decision circuit is a high speed D flip-flop. In

addition to the clock and data inputs, a user

adjustable decision threshold voltage is available. This

voltage is used to optimize the retimed data. The CDR

threshold and phase shifter do not require adjustment

over the temperature and input data level ranges.

The clock output of the CDR is a low spurious

sinusoidal signal and the complementary data outputs

are AC coupled ECL signals. DC coupled ECL

compatible data outputs are available.

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