8169 datasheet(9/30 Pages) STMICROELECTRONICS

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STA304A

4.0 I2S OUTPUT INTERFACE CONFIGURATION

In order to configure the I2S output interface the

Configuration Register B (CRB) can be used. Using the 3

I2SO_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of

them.

By default standard I2S output interface master is provided (mode 1 in bits 8,9,10 of register CRB,

I2SO_BICK_Pol = 1 and I2SO_LRCK_Pol = 0 in the same register)

4.1 Switching characteristics (10 pf load; Fsm=48 KHz):

Figure 3.

MODE

# of SLOTS

W. LENGHT

ALIGNMENT

DELAY SLOT

NOTES

Left

Yes

Right

MSb first only

Right

Left

Slave only

Not valid

Reserved, do not use.

Right

MSb first only. Slave only

Right

Slave only

SCKO frequency (master mode):

64 Fsm

(slave mode):

64 Fsm

SCKO pulse width low (T0) (slave mode):

min 40 ns.

SCKO pulse width high (T1) (slave mode):

min 40 ns.

SCKO active to LRCKO edge delay (T2):

min 20 ns.

SCKO active to LRCKO edge setup (T3):

min 20 ns.

SDO valid to SCKO active setup (T4):

min 20 ns.

SCKO active to SDO hold time (T5):

min 20 ns.

SCKO falling to LRCKO edge (T6) (master mode):

min 2 ns; max 8 ns.

SCKO falling to SDO edge(T7) (master mode):

min 2 ns; max 8 ns.

(slave mode):

min 6 ns; max 17 ns

D00AU1245

LRCKO

BICKO

SDO

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