CS5471

4

Notes: 4. All outputs unloaded. All inputs CMOS level.

5. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3V, AGND = DGND = 0V, VA- = -2V

(using charge-pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto

the VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-.

Instantaneous digital output data words are then collected for the channel under test. From these data

samples, the rms value (standard deviation) of the digital sinusoidal output signal is calculated, and this

rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need

to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage

is then defined as Veq. PSRR is then (in dB)

VA- = -2 V ±10%; AGND, DGND = 0.0 V) (See Note 6)

Notes: 6. All measurements performed under static conditions.

7. For OWRS and GAIN pins, input leakage current is 30 µA (Max).

Parameter

Symbol

Min

Typ

Max

Unit

Reference Output

Output Voltage

REFOUT

1.15

-

1.25

V

Temperature Coefficient

-

20

50

ppm/°C

Load Regulation

(Output Current 1

µA Source or Sink)

-6

10

mV

Power Supply Rejection

PSRR

60

-

-

dB

Reference Input

Input Voltage Range

VREF+

1.15

1.2

1.25

V

Input Capacitance

-

-

10

pF

Input CVF Current

-

-

1

µA

Power Supplies

Power Supply Currents

PSCA

PSCD

-

-

-

-

1.5

2.5

mA

mA

Power Consumption

(Note 4)

PC

-

-

15

mW

Power Supply Rejection

(DC, 50, 60 Hz)

(see Note 5)

PSRR

60

-

-

dB

Parameter

Symbol

Min

Typ

Max

Unit

High-Level Input Voltage

0.6 VD+

-

VD+

V

Low-Level Input Voltage

0.0

-

0.8

V

High-Level Output Voltage

(VD+) - 1.0

-

-

V

Low-Level Output Voltage

--

0.4

V

Input Leakage Current

(Note 7)

-±1

±10

µA

3-State Leakage Current

--

±10

µA

Digital Output Pin Capacitance

-9

-

pF

PSRR

20

106.07

V

eq

----------------







log

⋅

=