IXHQ100PI datasheet(8/9 Pages) IXYS

8 / 9 page

Fault Operation

ault Operation

When the output load current is such that the

voltage drop across the current sense resistor

between the SOURCE pin and the AGND

exceeds VCL (internally set to ~120 mv), the

GATE output is driven low to turn off the external

Power MOSFET connected between the load

and -V

in.

An external capacitor connected

between OFFTM pin and AGND pin determines

the off time T

off-delay. IXHQ100 will restart the turn

on sequence of the external Power MOSFET

with a load voltage slope determined by the

size of the external capacitor that is connected

to the SLOPE pin.

Shor

Short Cir

t Cir

t Circuit Pre

cuit Pre

cuit Prevention

vention

Restar

Restart Operation

t Operation

IXHQ 100PI

IXHQ 100SI

Vcc, then GSNSin pin can be used to detect

the presence or absence of -Vin. If INV is

connected to AGND, then GSNSin pin can be

used to detect the presence or absence of

Gnd.

COMP2 output goes high whenever an

overcurrent or a short circuit condition is

detected. The inverting input to COMP2 is

connected to the VCL output pin which is

internally set at approximately 120mV.

shown in Figure 1, one side of R4 is in series

with the source of Q1, the drain output of which

drives the load connected to J8. The return

side of R4 is connected to -Vin through J1. For

R4 = 0.02

Ω, Q1 source currents greater than

6A will turn on COMP2 and will be considered

either an overcurrent or short circuit event.

COMP3 goes high whenever the voltage at

OUTsns with respect to AGND becomes less

than 0.1*VCL(approximately 12mV). This can

only occur if either the current drawn by the driven

load is less than 600mA (12mV/.02) or -V

IN is

disconnected. This Auto-Disconnect technique

automatically detects load disconnections

without needing additional sensors.

Thus the SRFF1 will reset when one of the

following events occur:

1. Loss of AGND or -Vin.

2. Overcurrent or short circuit.

3. Auto-Disconnection

A valid S input into SRFF1 will immediately

drive its output, Q1, to high and will turn on both

N5 and N4. N5, an open drain output, will result

in RSTout being driven low. A current limiting

resistor, R1, in series with a 4N35 LED

connected to V

(fig 1)

can be used to

generate an isolated reset pulse. Turning on

N4 will discharge C7 and the internal 10pF

capacitor (fig 2). As soon as V

OFFTM drops below

DROP

=~0.9V, COMP4 in Figure 2 will turn on

through NOR1 and NOR2, and resets SRFF1

with a high applied to its R input. This act will

then turn off both N5 and N4 and allow OFFTM

pin to initiate its positive ramp as a result of I6

charging the capacitors C7 (Figure 1) and C2

(Figure 2) connected to the OFFTM pin.

The IXHQ100 will automatically attempt to

restart once a disconnection and reconnection

is detected. Either PUR or COMP4 going high

will reset SRFF1 during normal operation of

the IXHQ100 (fig 2). Resetting SRFF1 turns off

N4 and N5, and the OFFTM pin ramps up in

response. During this ramp, as long as V

OFFTM

is less than Vrf=~4.5V, COMP1 will keep N3 on

and C1 (Figure 2) and C8 (Figure 1) discharged.

After T

off-delay, VOFFTM is at Vrf, COMP1 output

then goes low, turning off N3. Now the SLOPE

pin is free to ramp up as a result of I5 charging

C1 (Figure 2) and C8 (Figure 1). The two unity-

gain buffers, OA4 and OA5, reflect V

SLOPE at the

GATE output pin during this positive ramp. As

soon as V

GATE overcomes the VQ1th, normal

operation is resumed.

When the IXHQ100 detects a short in the load,

a restart is automatically initiated. The GOUT

drops to zero and waits one T

off-delay before

SLOPE ramps up. As before, normal operation

is resumed.

IXHQ100PI Datasheet(PDF) 8 Page - IXYS Corporation

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