1

PS8418B

05/21/01

1

2

3

4

CLK_OUT

CLK_IN

GND

FB_IN

8

7

6

5

AGND

S

ProductPinConfiguration

Logic Block Diagram

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PI6C2302

ProductFeatures

• 2X CLK_INonCLK_OUT

• High-PerformancePhase-Locked-LoopClockDistribution

for Networking, ATM, 100/134 MHz Registered DIMM

Synchronous DRAM modules for server/workstation/

PC applications

• Zero Input-to-Output delay

• Lowjitter:Cycle-to-Cyclejitter±100psmax.

• On-chip series damping resistor at clock output drivers

for low noise and EMI reduction

• Wide range of Clock Frequencies

• Package:

Plastic 8-pin SOIC Package (W)

Phase-Locked Loop Clock Driver

ProductDescription

The PI6C2302 features a low-skew, low-jitter, phase-locked loop

(PLL) clock driver. By connecting the feedback CLK_OUT output

to the feedback FB_IN input, the propagation delay from the

CLK_INinputtoanyclockoutputwillbenearlyzero.ThePI6C2302

provides 2X CLK_IN on CLK_OUT output.

Application

If the system designer needs more than 16 outputs with the features

just described, using two or more zero-delay buffers such as

PI6C2509Q,andPI6C2510Q,islikelytobeimpractical.Thedevice-

to-device skew introduced can significantly reduce the perfor-

mance. Pericom recommends the use of a zero-delay buffer and an

eighteen output non-zero-delay buffer. As shown in

Figure 1, this combination produces a zero-delay buffer with all the

signal characteristics of the original zero-delay buffer, but with as

many outputs as the non-zero-delay buffer part. For example, when

combined with an eighteen output non-zero delay buffer, a system

designer can create a seventeen-output zero-delay buffer.

Figure1.ThisCombinationProvidesZero-DelayBetweenthe

Reference Clocks Signal and 17 Outputs

17

Zero Delay

Buffer

PI6C2302

Reference

Clock

Signal

CLK_OUT

Feedback

18 Output

Non-Zero

Delay

Buffer

ControlInput

Se

c

r

u

o

S

t

u

p

t

u

On

w

o

d

t

u

h

S

L

L

P

1L

L

PN

0N

I

_

K

L

CY

CLK_IN

FB_IN

S

PLL

CLK_OUT

÷2

8-Pin

W