VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7146

2.5Gb/s, 20-Bit Transceiver

Page 6

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

8/28/00

G52162-0 Rev. 2.7

Figure 4: Transmit Timing Waveforms

Table 3: Transmit AC Characteristics

Parameters

Description

Min

Typ

Max

Units

Conditions

T[0:19] setup time to the rising

edge of TBC

1.5

—ns

Measured between the valid

data level of T[0:19] to the

1.4V point of TBC.

T[0:19] hold time after the rising

edge of TBC

1.0

—

ns

TX+/TX- rise and fall time

—

160

ps

20% to 80% into 50

Ω load to

Tested on a sample basis.

Latency from rising edge of TBC

to T0 appearing on TX+ TX-

24 bc

+1ns

45 bc

+1ns

Bit

Clock

Bit clock periods

(PLL locked)

Transmitter Output Jitter Allocation

Serial data output random jitter

(RMS)

—

5

7.5

ps

RMS, tested on a sample basis.

Serial data output deterministic

jitter (p-p)

—25

30

ps

Peak-to-peak, tested on a

sample basis.

Data Valid

T[0:19]

20-Bit Data

TBC

Data Valid

Data Valid