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THS1040 Datasheet(PDF) 21 Page - Texas Instruments |
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THS1040 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 32 page ![]() THS1040 SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004 21 www.ti.com PRINCIPLES OF OPERATION onboard reference generator configuration (continued) _ + VBG ADC References Buffer A2 MODE = REFSENSE AGND VREF = External AVDD _ + AVDD 2 or AVDD Figure 28. Drive VREF Mode operating configuration examples Figure 29 shows a configuration using the internal ADC references for digitizing a single-ended signal with span 0 V to 2 V. Tying REFSENSE to ground gives 1 V at pin VREF. Tying MODE to AVDD/2 then sets the REFT and REFB voltages via the internal reference generator for a 2-Vp-p ADC input range. The VREF pin provides the 1-V mid-scale bias voltage required at AIN−. VREF should be well decoupled to AGND to prevent sample-and-hold switching at AIN− from corrupting the VREF voltage. AIN+ AIN− VREF = 1 V REFB MODE REFSENSE AVDD/2 2 V 0 V 1 V REFT 20 Ω 20 Ω 20 pF 10 µF 0.1 µF 0.1 µF 10 µF 0.1 µF 20 pF Figure 29. Operating Configuration: 2-V Single-Ended Input, Internal ADC References |
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