THS1040

SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004

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APPLICATION INFORMATION

driving the THS1040 analog inputs

driving the clock input

Obtaining good performance from the THS1040 requires care when driving the clock input.

Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should

ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as

possible in which to operate.

The CLK pin should also be driven from a low jitter source for best dynamic performance. To maintain low jitter

at the CLK input, any clock buffers external to the THS1040 should have fast rising edges. Use a fast logic family

such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other

logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.

voltage to drive above and below this level.

driving the sample and hold inputs

driving the AIN+ and AIN− pins

Figure 32 shows an equivalent circuit for the THS1040 AIN+ and AIN− pins. The load presented to the system

C1

8 pF

AVDD

AGND

CLK

CLK

C2

1.2 pF

1.2 pF

CSample

VCM = AIN+/AIN− Common Mode Voltage

AIN

_

+

Figure 32. Equivalent Circuit for Analog Input Pins AIN+ and AIN−

circuit modelled as an equivalent resistor:

R

IN2 +

1

C

S

f

CLK

resistance for high impedance sources.

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