AD9925BBCZRL datasheet(46/96 Pages) AD

46 / 96 page

AD9925

Rev. A | Page 46 of 96

The AD992

rmance ADC architecture, opti-

r high sp

low power. Diff

inearity

NL) performan

is typically better than 0.5 LSB. The ADC

put r

. See Figure 10, Figu

, and Figure 13

typical linearit

nd noise performanc

s for the

9925.

ptical Black Clamp

used to remove residual offsets

in the signa

low frequency variations in the

evel

the optical blac

ixel in-

val on each lin

e ADC output is com

d with a fixed

vel referen

elected by the user

clamp level

ister. The value can be programmed be

n 0 LSB and

LSB in 256 st

esulting error

iltered to

educe noise, and the correction value is applied to the ADC

put through a DAC. Normally, the optical black clamp loop is

e, but this loop can be updated

more slowly

lar application. If external digital

ing is used

he postprocessin

optical

ping m

e disabled using Bit

the OPRMODE

ister. When th

p is disabled, the cla

evel register may

l be used to pr

e programmable off

djustment.

B pulse should be placed durin

e CCD’s optical

lack pixels. It is recommended that the CLPOB pulse duration

pulse widths may be used, but

the ability t

ncy variations in the black level

e reduced. Se

orizontal Clam

ing

tion for timing examples.

The AD9925

ta is latched using the DOUT

E register valu

wn in Figure 55

im-

own in Figu

1 and Figure 22. It is

possible to

ve the output latc

transparent, so that t

ata outputs are

d immediately fr

the ADC. Programm

the AFE

NTROL Register

to a 1 will set th

put latches

ansparent. The data outputs can also be disabled (three stated)

ister Bit D3 to a 1.

The switchin

puts can couple noise back to the

signal path. T

ze any switchi

ec-

mended that the

UT PHASE register

t to the same

e as the SHP sam

g location, or up to

es after the

P sampling locati

ther settings can pr

e good results,

perimentation

ecessary. It is recommended that the

OUT PHASE location not occur between the SHD sampling

cation and 12 edges after the SHD location. For example, if

E should be set to an edge

greater. If adjustable phase is not required for

ta outputs, the output latch

ansparent using

ister 0x03, Bit [4].

The data output coding is normally straight binary, but the

oding may be changed to gray coding by setting the AFE

ADC

5 uses high perfo

mized fo

eed and

erential nonl

uses a 2 V in

ange

re 12

for

y a

e plot

The optical black clamp loop is

l chain and to track

CCD’s black l

. During

k (shielded) p

ter

e, th

pare

black le

ce, s

in the

reg

twee

255

eps. The r

signal is f

turned on once per horizontal lin

to suit a particu

clamp

during t

g, the AD9925

black clam

ay b

D2 in

reg

e loo

mp l

stil

ovid

set a

The CLPO

g th

be at least 20 pixels wide. Shorter

o track low freque

will b

e the H

ping and Blank

sec

Digital Data Outputs

digital output da

PHAS

e, as sho

. Output data t

ing is sh

re 2

also

lea

hes

he d

vali

ing

Bit D4

e out

by setting the AFE CONTROL Reg

g of the data out

analog

o minimi

ng noise, it is r

be se

edg

plin

12 edg

on. O

oduc

but ex

is n

SHDLOC = 0, then DOUT PHAS

location of 12 or

the da

can be left tr

reg

CONTROL Register Bit D5 to a

AD9925BBCZRL Datasheet(PDF) 46 Page - Analog Devices

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