6

SAM0358-052201

ESS Technology, Inc.

ES4428/ES4427 PRODUCT BRIEF

Name

Number

I/O

Definition

AUX8

18

I/O

General purpose I/O.

TWS

19

I

Transmit audio frame sync.

SPLL_OUT

O

SPLL_OUT is the select PLL output.

AUX9

20

I/O

General purpose I/O.

TSD

21

I

Transmit audio data input.

TBCK

22

I

Transmit audio bit clock.

RWS

23

O

Receive audio frame sync.

SEL_PLL1

I

System and DSCK output clock frequency selection at reset time. The matrix

below lists the available clock frequencies and their respective PLL bit settings..

RSTOUT#

24

O

Reset output.

RSD

33

O

Receive audio data input.

SEL_PLL0

I

Refer to the description and matrix for SEL_PLL1 pin 23.

AUX10

34

I/O

General purpose I/O.

AUX11

35

I/O

Interrupt output to ES4428.

AUX12

36

I/O

CD loader C2PO.

RBCK

37

O

Receive audio bit output clock.

SER_IN

I

SER_IN is the serial input DSC mode. 1 = Serial DSC mode. 0 = Parallel DSC

mode.

AUX13

38

I/O

General purpose I/O.

AUX14

39

I/O

Interrupt input from Modem DSP.

AUX15

40

I/O

IR interrupt Input.

VSSAA

41,51

I

Audio analog ground.

VCM

42

I

ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25

V. Bypass to analog ground with 47

µF electrolytic in parallel with 0.1 µF.

VREFP

43

I

DAC and ADC maximum reference. Bypass to VCMR with 10

µF in parallel with 0.1

µF.

VCCAA

44

I

5.0V analog audio power supply.

AOR+,

AOR-

45, 46

O

Right channel output.

AOL-, AOL+

47, 48

O

Left channel output.

MIC2

49

I

Microphone input 2.

MIC1

50

I

Microphone input 1.

VREF

52

I

Internal resistor divider generates Common Mode Reference (CMR) voltage.

Bypass to analog ground with 0.1

µF.

VREFM

53

I

DAC and ADC minimum reference. Bypass to VCMR with 10

µF in parallel

with 0.1

µF.

RSET

54

I

Full scale DAC current adjustment.

COMP

55

I

Compensation pin.

VSSAV

56:57, 62:63

I

Video analog ground

CDAC

58

O

Modulated chrominance output.

VCCAV

59, 60

I

Video VCC, 5 V

Table 2

ES4427 Pin Descriptions (Continued)

SEL_PLL1

SEL_PLL0

DCLK

0

0

Bypass PLL (input mode)

0

1

27 MHz (output mode) Default

1

0

32.4 MHz (output mode)

1

1

40.5 MHz (output mode)