FDMF3035 datasheet(13/21 Pages) ONSEMI

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Synchronous Buck Operating Modes

Continuous Current Mode with Positive

Inductor Current (CCM1)

This condition is typical of a moderate-to-heavily loaded

power stage. During this mode, the inductor current is

always flowing towards the output capacitor. The high-

side MOSFET is hard-switching during the turn-on and

turn-off

events.

The

low-side

MOSFET

acts

synchronous rectifier.

Continuous Current Mode with Negative

Inductor Current (CCM2)

This operating mode can occur during two situations:

1.) A converter load transient may force the power

stage to pull energy from the output capacitors and

deliver the energy back to the input capacitors (Boost

Mode). This situation is common in synchronous buck

applications

that

require

output

voltage

load-line

positioning.

During this mode, the negative inductor current (current

flowing into FDMF3035 SW node) may become large

and persist for many cycles. This situation causes the

low-side MOSFET to hard switch and the high-side

MOSFET acts as a synchronous rectifier. It is highly

recommended to check peak SW node voltage stress

during any situation that can generate large negative

inductor currents.

2.) A power stage that is operating in forced CCM

mode with lighter converter loads. Here, the inductor

peak-to-peak ripple current is greater than two times the

load current and the inductor current is flowing both

positive and negative in a switching cycle.

Discontinuous Current Mode (DCM)

This condition is typical of a lightly loaded power stage.

During DCM, the high-side MOSFET turns on into an

un-energized out filter inductor (i.e. zero inductor

current). The inductor current ramps up during the high-

side MOSFET on-time and is then allowed to ramp back

down to aero amps during the low-side on-time (i.e

inductor current returns to zero every switching cycle.

High-Side Driver

The high-side driver (HDRV) is designed to drive a

floating N-channel MOSFET (Q1). The bias voltage for

the high-side driver is developed by a bootstrap supply

circuit, consisting of the internal Schottky diode and

external bootstrap capacitor (CBOOT). During startup, the

SW node should be held at PGND, allowing CBOOT to

charge to PVCC through the internal bootstrap diode.

When the PWM input goes HIGH, HDRV begins to

charge the gate of the high-side MOSFET (internal GH

pin). During this transition, the charge is removed from

the CBOOT and delivered to the gate of Q1. As Q1 turns

on, SW rises to VIN, forcing the BOOT pin to VIN +

VBOOT, which provides sufficient VGS enhancement for

Q1. To complete the switching cycle, Q1 is turned off by

pulling HDRV to SW. CBOOT is then recharged to PVCC

when the SW falls to PGND. HDRV output is in phase

with the PWM input. The high-side gate is held LOW

when the driver is disabled or the PWM signal is held

within the 3-state window for longer than the 3-state

hold-off time, tD_HOLD-OFF.

Low-Side Driver

The low-side driver (LDRV) is designed to drive the

gate-source

ground-referenced,

low-RDS(ON),

N-channel MOSFET (Q2). The bias for LDRV is

internally connected between the PVCC and AGND.

When the driver is enabled, the driver output is 180° out

of phase with the PWM input. When the driver is

disabled (FCCM = 0 V), LDRV is held LOW.

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