Description
Output Features
DDR I/DDR II Zero Delay Clock Buffer
• Low skew, low jitter PLL clock driver
• Max frequency supported = 400MHz (DDRII 800)
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Programmable skew through SMBus
• Frequency defect control thorugh SMBus
• Individual output control programmable through SMBus
Key Specifications
• CYCLE - CYCLE jitter: <100ps
• OUTPUT - OUTPUT skew: <100ps
• DUTY CYCLE: 48% - 52%
• 28-pin SSOP package
• Available in RoHS compliant packaging
• Operates @ 2.5V or 1.8V