IDTTM/ICSTM

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935

REV H

12/1/08

ICS9P935

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

5

Notes:

1.

Refers to transition on noninverting output in PLL bypass mode.

2.

While the pulse skew is almost constant over frequency, the duty cycle error increases at

higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc)

decreases as the frequency goes up.

3.

Switching characteristics guaranteed for application frequency range.

4.

Static phase offset shifted by design.

Timing Requirements

TA = 0 - 70°C Supply Voltage AVDD, VDD = 1.8 V +/- 0.1V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Max clock frequency

freqop

1.8V+0.1V @ 25°C

125

500

MHz

Application Frequency

Range

freqApp

1.8V+0.1V @ 25°C

160

400

MHz

Input clock duty cycle

dtin

40

60

%

CLK stabilization

TSTAB

15

µs

Switching Characteristics

1

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Output enable time

ten

OE to any output

8

ns

Output disable time

tdis

OE to any output

8

ns

Period jitter

tjit (per)

-40

40

ps

Half-period jitter

tjit(hper)

-75

75

ps

Input Clock

1

2.5

4

v/ns

Output Enable (OE), (OS)

0.5

v/ns

Output clock slew rate

SLr1(o)

1.5

2.5

3

v/ns

tjit(cc+)

040

ps

tjit(cc-)

0

-40

ps

Dynamic Phase Offset

t( )dyn

-50

50

ps

Phase error

t(phase error)

2

-50

0

50

ps

Output to Output Skew

tskew

40

ps

SSC modulation frequency

30.00

33

kHz

SSC clock input frequency deviation

0.00

-0.50

%

Cycle-to-cycle period jitter

Input slew rate

SLr1(i)