LPS33HW datasheet(37/50 Pages) STMICROELECTRONICS

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LPS33HW

8.6

CTRL_REG2 (11h)

Control register 2

The BOOT bit is used to refresh the content of the internal registers stored in the Flash

memory block. At device power-up the content of the Flash memory block is transferred to

the internal registers related to the trimming functions to allow correct behavior of the device

itself. If for any reason the content of the trimming registers is modified, it is sufficient to use

this bit to restore the correct values. When the BOOT bit is set to ‘1’, the content of the

internal Flash is copied inside the corresponding internal registers and is used to calibrate

the device. These values are factory trimmed and they are different for every device. They

allow correct behavior of the device and normally they should not be changed. At the end of

the boot process the BOOT bit is set again to ‘0’ by hardware. The BOOT bit takes effect

after one ODR clock cycle.

SWRESET is the software reset bit. The following device registers (INTERRUPT_CFG

(0Bh), THS_P_L (0Ch), THS_P_H (0Dh), CTRL_REG1 (10h), CTRL_REG2 (11h),

CTRL_REG3 (12h), FIFO_CTRL (14h), REF_P_XL (15h), REF_P_L (16h), REF_P_H

(17h)) are reset to the default value if the SWRESET bit is set to '1'. The SWRESET bit

returns back to '0' by hardware.

The ONE_SHOT bit is used to start a new conversion when the ODR[2,0] bits in

CTRL_REG1 (10h) are set to ‘000’. Writing a ‘1’ in ONE_SHOT triggers a single

measurement of pressure and temperature. Once the measurement is done, the

ONE_SHOT bit will self-clear, the new data are available in the output registers, and the

STATUS (27h) bits are updated.

BOOT

FIFO_EN

STOP_ON_FTH

IF_ADD_INC

I2C_DIS

SWRESET

0(1)

ONE_SHOT

1. This bit must be set to ‘0’ for proper operation of the device

BOOT

Reboot memory content. Default value: 0

(0: normal mode;

1: reboot memory content). The bit is self-cleared when the BOOT is completed.

FIFO_EN

FIFO enable. Default value: 0

(0: disable; 1: enable)

STOP_ON_FTH

Stop on FIFO threshold. Enable FIFO watermark level use. Default value: 0

(0: disable; 1: enable)

IF_ADD_INC(1)

1. It is recommend to use a single-byte read (with IF_ADD_INC = 0) when output data registers are acquired

without using the FIFO. If a read of the data occurs during the refresh of the output data register, it is

recommended to set the BDU bit to ‘1’ in CTRL_REG1 (10h) in order to avoid mixing data.

serial interface (I2C or SPI). Default value: 1

(0: disable; 1: enable)

I2C_DIS

Disable I2C interface. Default value: 0

(0: I2C enabled;1: I2C disabled)

SWRESET

Software reset. Default value: 0

(0: normal mode; 1: software reset).

The bit is self-cleared when the reset is completed.

ONE_SHOT

One-shot enable. Default value: 0

(0: idle mode; 1: a new dataset is acquired)

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