SSD1850 datasheet(23/56 Pages) ETC

23 / 56 page

SSD1850/51 Series

Rev 1.2

01/2003

SOLOMON

3. Bias Divider

If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block

will divide the regulator output (VL6) to give the LCD driving levels (VL2 -VL5).

A low power consumption circuit design in this bias divider saves most of the display current comparing to

traditional design.

Stabilizing Capacitors (0.47~2uF) are required to be connected between these voltage level pins (VL2 -

VL5) and VSS. If the LCD panel loading is heavy, four additional resistors are suggested to add to the

application circuit as following:

4. Contrast Control

Software control of 64 voltage levels of LCD voltage.

5. Bias Ratio Selection circuitry

Software control of 1/4 to 1/10 bias ratio to match the characteristic of LCD panel.

Note: SSD1850 has 1/4 to 1/9 bias only.

6. Self adjust temperature compensation circuitry

Provide 2 different temperature compensation grade selections to satisfy the various liquid crystal

temperature grades. The grading can be selected by software control.

Default temperature coefficient (TC) value is -0.05%/

°C.

193 / 209 Bit Latch

A register carries the display signal information. In 128X65/81 display mode, data will be fed to the HV-

buffer Cell and level-shifted to the required level.

Level Selector

Level Selector is a control of the display synchronization.

Display voltage can be separated into two sets and used with different cycles. Synchronization is

important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the

COM or SEG LCD waveform.

HV Buffer Cell (Level Shifter)

HV Buffer Cell works as a level shifter which translates the low voltage output signal to the required

driving voltage. The output is shifted out with an internal FRM clock which comes from the Display Timing

Generator. The voltage levels are given by the level selector which is synchronized with the internal M

signal.

Connections for heavy loading applications

VSS

VL2

VL3

VL4

VL5

VL6

VSS

Remarks:

1. C2 = 0.47~2.0uF

2. RL = 100K~1M (Optional)

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