SSD1850 datasheet(24/56 Pages) ETC

24 / 56 page

SSD1850/51 Series

Rev 1.2

01/2003

SOLOMON

Reset Circuit

When RES input is low, the chip is initialized to the following:

1. Page address is set to 0

2. Column address is set to 0

3. Display is OFF

4. Display Start Line is set to 0 (GDDRAM page 0, D0)

5. Display Offset is set to 0 (COM0 is mapped to ROW0)

6. 128x80 display mode for SSD1851 and 128x64 display mode for SSD1850.

7. Normal/Reverse Display is Normal

8. N-line Inversion Register is 0

9. Entire Display is OFF

10. Power Control Register (VC, VR, VF) is set to (0,0,0)

11. 3X Booster is selected

12. Internal Resistor Ratio register is set to 0H

13. Software Contrast is set to 32

14. LCD Bias Ratio is set to 1/10 for SSD1851 and 1/9 for SSD1850.

15. Normal scan direction of COM outputs

16. Segment remap is disabled (SEG0 display column address 0)

17. Internal oscillator is OFF

18. Test mode is OFF

19. Temperature coefficient is set to PTC0 (-0.05%)

20. Icon display line is OFF

When RESET command is issued, the following parameters are initialized only:

1. Page address is set to 0

2. Column address is set to 0

3. Initial Display Line is set to 0 (point to display RAM page 0, D0)

4. Internal Resistor Ratio register is set to 0H

5. Software Contrast is set to 32

SSD1850 Datasheet(PDF) 24 Page - List of Unclassifed Manufacturers