MCP6S21 datasheet(7/43 Pages) MICROCHIP

7 / 43 page

 2003 Microchip Technology Inc.

DS21117A-page 7

MCP6S21/2/6/8

1.1

DC Output Voltage Specs / Model

1.1.1

IDEAL MODEL

The ideal PGA output voltage (VOUT) is:

EQUATION

(see Figure 1-7). This equation holds when there are

no gain or offset errors and when the VREF pin is tied to

a low impedance source (<< 0.1

Ω) at ground potential

(VSS = 0V).

1.1.2

LINEAR MODEL

The PGA’s linear region of operation, including offset

and gain errors, is modeled by the line VO_linear, shown

in Figure 1-7.

EQUATION

The endpoints of this line are at VO_ideal =0.3V and

VDD-0.3V. The gain and offset specifications referred to

in the electrical specifications are related to Figure 1-7,

as follows:

EQUATION

FIGURE 1-7:

Output Voltage Model with

the standard condition VREF = VSS = 0V.

1.1.3

OUTPUT NON-LINEARITY

Figure 1-8 shows the Integral Non-Linearity (INL) of the

output voltage.

EQUATION

The output non-linearity specification in the electrical

specifications is related to Figure 1-8 by:

EQUATION

FIGURE 1-8:

Output Voltage INL with the

standard condition VREF = VSS = 0V.

VO_ideal

GVIN

VREF

VSS

where: G is the nominal gain

VO_linear

G1 gE

() VIN 0.3V VOS

–

() 0.3V

VREF

VSS

100%

V2 V1

–

GVDD 0.6V

–

()

--------------------------------------

VOS

G1 gE

()

-------------------------

GTA

∆

⁄

∆

----------

G+1

0.3

VDD-0.3

VDD

VOUT (V)

VIN (V)

0.3

VDD - 0.3 VDD

INL

VOUT VO_linear

–

VONL

max V4 V3

{}

VDD 0.6V

–

---------------------------------

INL (V)

VIN (V)

0.3

VDD - 0.3 VDD

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