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LT3840

3840fa

For more information www.linear.com/LT3840

the bulk capacitance and RMS current capability. The bulk

capacitance will determine the supply input ripple voltage.

The RMS current capability is used to prevent overheating

the capacitor. The bulk capacitance is calculated based on

maximum input ripple, ΔVIN:

CIN(BULK) =

IOUT(MAX) • VOUT

ΔVIN • fSW • VIN(MIN)

ΔVIN is typically chosen at a level acceptable to the user.

A good starting point is 100mV to 200mV. Aluminum

electrolytic capacitors are a good choice for high voltage,

bulkcapacitanceduetotheirhighcapacitanceperunitarea.

The capacitor’s RMS current is:

ICIN(RMS) =IOUT

VOUT(VIN – VOUT)

(VIN)2

If applicable, calculate it at the worst-case condition,

VIN = 2VOUT. The RMS current rating of the capacitor

is specified by the manufacturer and should exceed the

calculated ICIN(RMS). Due to their low ESR (equivalent

series resistance), ceramic capacitors are a good choice

for high voltage, high RMS current handling. Note that the

ripplecurrentratingsfromaluminumelectrolyticcapacitor

manufacturersarebasedon2000hoursoflife.Thismakes

it advisable to further derate the capacitor or to choose

a capacitor rated at a higher temperature than required.

The combination of aluminum electrolytic capacitors and

ceramic capacitors is an economical approach to meeting

the input capacitor requirements. The capacitor voltage

rating must be rated greater than maximum VIN voltage.

Multiple capacitors may also be paralleled to meet size

or height requirements in the design. Locate the capaci-

tor very close to the MOSFET switch and use short, wide

PCB traces to minimize parasitic inductance. Use a small

(0.1μF to 1μF) bypass capacitor between the chip VIN pin

and GND, placed close to the LT3840.

Output Capacitor Selection

The output capacitance, COUT, selection is based on the

design’s output voltage ripple, ΔVOUT and transient load

requirements. ΔVOUT is a function of ΔIL and the COUT

ESR. It is calculated by:

∆VOUT = ∆IL • ESR+

8 • fSW •COUT

(

)









The maximum ESR required to meet a ΔVOUT design

requirement can be calculated by:

ESR(MAX)=

∆VOUT

(

) L() fSW

(

)

VOUT • 1–

VOUT

VIN(MAX)











Worst-case ΔVOUToccursatthehighestinputvoltage.Use

paralleled multiple capacitors to meet the ESR require-

ments. Increasing the inductance is an option to lower the

ESR requirements. For extremely low ΔVOUT,anadditional

LC filter stage can be added to the output of the supply.

Linear Technology’s Application Note 44 has some good

tips on sizing an additional output filter.

Output Voltage Programming

A resistive divider sets the DC output voltage according

to the following formula:

R2=R1

VOUT

1.250V

–1









The external resistor divider is connected to the output of

the converter as shown in Figure 6.

applicaTions inForMaTion

Figure 6. Output Voltage Feedback Divider

3840 F06

COUT

VOUT

Tolerance of the feedback resistors will add additional er-

ror to the output voltage. The VFB pin input bias current

is typically 5nA, so use of extremely high value feedback

resistors results in a converter output that is slightly

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