MTC20154

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The crystal’s exact oscillation frequency can be tuned around the nominal frequency. This is needed in

order to allow the system to minimize the clock phase shift between the LT and the NT modems. The in-

formation coming from the digital processor via the CTRLIN path is used to drive a 8 bits DAC (resistor

ladder architecture) which generates a control current. This current is externally converted and filtered to

generate the required control voltage for the varicap. The VCXO characteristics are given in the following

table.

Table 20. VCXO characteristics

PLL Based Frequency Doubler

Dual crystal frequency can now be used needed when a 17.644 MHz crystal with the MTC20154 on–board

crystal

is used. A frequency doubler, build driver. However, a master clock

up around a Phase Locked

Loop (PLL), frequency of 35.328 MHz is still

will then be used.

Digital Interface

Control Interface

The digital code setting for the MTC20154 configuration is sent over a serial line (CTRLIN) using the word

clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit (’0’), the

three LSBs being used to identify the data contained in the 12 remaining bits. Test related data are latched

but they are overruled by the normal settings if the TEST pin is low.

Control Interface Timing

The control interface bits are considered valid on each positive edge of the master clock (CLKM). They

will be sampled at this moment. The stop bit will trigger the internal data validation. The timing require-

ments are depicted in the following figure and table:

Figure 9. Control Interface Timing diagram

Data

Min

Typical

Max

Unity

Needed crystal accuracy

50

–

–

ppm

Needed crystal frequency tuning range

100

–

–

ppm

DAC resolution

-

8

-

bit

DAC output voltage range

–

AVDD/2

–

V

DAC differential non linearity error

–

–

1.5

LSB

DAC integrated non linearity error

–

–

4

LSB

VCXO nominal output current

(Rref = 16.5 K AVDD = 3.3 V)

95

100

105

mA

Power consumption

–

.225

–

mW

CLKM

CLKWD

CTRLIN

Start

bit

Th

ctrl data bits

ctrl cmd bits 1 stop bit (high)

Ts