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AS6200C

Register Description

Datasheet

• PUBLIC

DS000563

• v2-01 • 2018-Apr-13

35

│ 23

After the start condition, the slave address byte is transmitted which is completed with a ninth bit which

indicates a read (bit=’1’) or a write operation (bit=’0’) respectively. All slaves read the data on the rising

edge of the clock. An acknowledge signal is generated by the addressed slave during the ninth clock

pulse. This acknowledge signal is produced by pulling the pin SDA to a low level by the selected

slave.

Subsequently, the byte data transfer is started and finished by an acknowledge bit. A change in the

data signal (SDA) while the clock signal (SCL) is high causes a START or STOP condition. Hence, it

must be ensured such a condition is prevented during a data transfer phase.

After completing the data transfer, the master generates a STOP condition by pulling the data line

(SDA) from low level to high level while the clock signal (SCL) is kept at high level.

6.3.2

Data Interface

A bus connection is created by connecting the open drain input/output lines SDA and SCL to the two

wire bus. The inputs of SDA and SCL feature Schmitt-trigger inputs as well as low pass filters in order

to suppress noise on the bus line. This improves the robustness against spikes on the two wire

interface.

Both fast transmission mode (1kHz to 400kHz) and high-speed transmission mode (1kHz to 3.4MHz)

are employed to cover different bus speed settings.

Any data transfer transmits the MSB first and the LSB as last bit.

6.3.3

Bus Address

A slave address consists of seven bits, followed by a data direction bit (read/write operation). The

slave address can be selected from a pool of two different address settings by connecting the input pin

ADD0 to an appropriate signal as summarized in the following table.

The ADD0 must not be left unconnected.

Figure 26:

I²C Address Select Configuration

ADD0 connection

Device Address (bin)

Device Address (hex)

VSS

0100 1000

0x48

VDD

0100 1001

0x49

6.3.4

Read/Write Operation

In order to access an internal data register, the index register must be written in advance. This register

contains the actual register address and selects the appropriate register for an access. A typical