ISL9216, ISL9217

FN6488 Rev 1.00

Page 14 of 34

November 2, 2007

Registers

TABLE 1. REGISTERS

ADDR

REGISTER

READ/WRITE

7

6

5

4

3210

00H

Configuration

Status

Read only

CU

Cascade U

CL

Cascade L

Reserved

WKUP

WKUP pin

Status

Reserved

Reserved

Reserved

Reserved

01H

Operating Status

(Note 9)

Read only

Reserved

Reserved

XOT

Ext over

temp

IOT

Int over

Temp

LDFAIL

Load Fail

(VMON)

DSC

Short

Circuit

DOC

Discharge

OC

COC

Charge OC

02H

Cell Balance

Read/Write

CB7ON

CB6ON/

WKUPR

CB5ON

CB4ON

CB3ON

CB2ON

CB1ON

Reserved

Cell balance FET control bits (plus WKUP of ISL9217 in cascade)

03H

Analog Out

Read/Write

UFLG1

User Flag 1

UFLG0

User Flag 0

Reserved

Reserved

AO3

AO2

AO1

AO0

Analog output select bits

04H

FET Control

Read/Write

SLEEP

Force

Sleep

(Note 10)

LDMONEN

Turn on

VMON

connection

Reserved

Reserved

Reserved

Reserved

CFET

Turn on

Charge

FET

(Note 11)

DFET

Turn on

Disharge

FET

(Note 11)

05H

Discharge Set

Read/Write

(Write only if

DISSETEN bit

set)

DENOCD

OCDV1

OCDV0

DENSCD

SCDV1

SCDV0

OCDT1

OCDT0

Turn off

automatic

OCD

control

Configure Overcurrent

Discharge Threshold

Turn off

automatic

SCD control

Configure Short Circuit

Discharge Threshold

Configure Overcurrent

Discharge Time-out

06H

Charge Set

Read/Write

(Write only if

CHSETEN bit

set)

DENOCC

OCCV1

OCCV0

SCLONG

Long Short-

circuit delay

CTDIV

Divide

charge

time by 32

DTDIV

Divide

discharge

time by 64

OCCT1

OCCT0

Turn off

automatic

OCC

control

Configure Overcurrent

Charge Threshold

Configure Overcurrent

Charge Time-out

07H

Feature Set

Read/Write

(Write only if

FSETEN bit

set)

ATMPOFF

Turn off

automatic

external

temp scan

DIS3

Disable 3.3V

reg. (device

requires

external

3.3V)

TMP3ON

Temp 3.3V

keep on

DISXTSD

Disable

external

thermal

shutdown

DISITSD

Disable

internal

thermal

shutdown

POR

Force POR

DISWKUP

Disable

WKUP pin

WKPOL

Wake-up

Polarity

08H

Write Enable

Read/Write

FSETEN

Enable

Feature

Set writes

CHSETEN

Enable

Charge Set

writes

DISSETEN

Enable

Discharge

Set writes

UFLG3

User Flag 3

UFLG2

User Flag 2

Reserved

Reserved

Reserved

09H:

FFH

Reserved

NA

RESERVED

NOTES:

7. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.

8. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, 6, 7, and 8: write a reserved bit

with the value “0”. Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation.

9. These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared.

10. This SLEEP bit is cleared on initial power-up, by the WKUP pin going high (when WKPOL = ”1”) or by the WKUP pin going low (when

11. When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turns

drive output circuit (though not the actual voltage at the output pin).

12. The shaded registers are not used in the ISL9217 device. Shaded status registers return ‘0’ when read. Shaded “read/write” registers can be read

and written, but they provide no functionality. When writing to the shaded areas in the ISL9217, the locations must be written as “0”.